1. Field of the Invention
The present invention relates to semiconductor integrated circuits and more particularly to a semiconductor integrated circuit capable of reducing an area occupied by a data bus.
2. Description of the Background Art
A data bus in a conventional semiconductor integrated circuit has a structure as shown in FIG. 10. A semiconductor integrated circuit 600 includes a first bank 610, a first input/output circuit 640, a second bank 650, a second input/output circuit 660, data buses 690, 700, and circuits 710, 720. First bank 610 is divided into a first block 620 and a second block 630, and second bank 650 is divided into a first block 670 and a second block 680. First block 620 of first bank 610 and second block 680 of second bank 650 include memory cells inputting/outputting data through input/output terminals DQ0 to 7, and second block 630 of first bank 610 and first block 670 of second bank 650 include memory cells inputting/outputting data through input/output terminals DQ8 to 15.
First and second input/output circuits 640, 660 are each formed of an amplification circuit (PA), a write buffer (WB), and a read driver (RDRV). The amplification circuits (PA) amplify data read out from the memory cells included in first and second blocks 620, 630, 670, 680 of first and second banks 610, 650. The read drivers (RDRV) output the data amplified by the amplification circuits (PA) to data buses 690, 700. The write buffers (WB) receive data input from input/output terminals DQ0 to 15 through data buses 690, 700, and write the received data to the memory cells included in first and second blocks 620, 630, 670, 680 of first and second banks 610, 650. Circuits 710, 720 are each formed of a pad or an input/output interface circuit.
Data bus 690 is connected to the memory cells inputting/outputting data through input/output terminals DQ8 to 15, and data bus 700 is connected to the memory cells inputting/outputting data through input/output terminals DQ0 to 7. Therefore, data bus 700 is arranged to extend along first block 620 of first bank 610, pass through a point A between circuits 710 and 720, and extend along second block 680 of second bank 650. In addition, data bus 690 is arranged to extend along first block 670 of second bank 650, pass through point A between circuits 710 and 720, and extend along second block 630 of first bank 610.
Since data buses 690, 700 each transmit 8-bit data, they are formed of eight pairs of data buses DB0, /DB0 to DB7, /DB7 as shown in FIG. 11. Data buses 690 and 700 cross at one point A.
Semiconductor integrated circuit 600 having sixteen input/output terminals DQ has been described as an example. If the number of input/output terminals DQ is increased to over sixteen, the area occupied by data buses is increased in the conventional data bus structure in which the data buses cross at one point.
If the interval of the data buses is made smaller to reduce the occupied area of the data buses, coupling capacitance causes noise between the adjacent data buses as shown in FIG. 11, making it impossible to correctly input/output data to/from memory cells.
Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of reducing the occupied area of data buses.
Another object of the present invention is to provide a semiconductor integrated circuit capable of suppressing noise from an adjacent data bus.
A semiconductor integrated circuit according to the present invention includes first and second banks having a plurality of memory cells and capable of being driven independently, a first input/output circuit writing/reading data to/from the plurality of memory cells included in the first bank, a second input/output circuit writing/reading data to/from the plurality of memory cells included in the second bank, data buses arranged between the first and second banks and connected to the first and second input/output circuits, and a plurality of circuits arranged between the first and second banks and exchanging data with the data buses, the data buses crossing between adjacent two circuits of the plurality of circuits.
In the semiconductor integrated circuit according to the present invention, the data buses for outputting data read out from the memory cells cross between adjacent two circuits of the plurality of circuits arranged between the first and second banks, and a small number of data buses cross at each crossing. Therefore, the area occupied by the data buses at the crossing can be suppressed.
Preferably, the data buses have such number of crossings that is determined based on the number of blocks obtained by dividing the first and second banks.
When there are a large number of blocks obtained by dividing the banks, the number of crossings is made larger and each data bus comprising the data buses occupies a small area at the crossing. Therefore, the area occupied by the data bus at each crossing can be suppressed.
Preferably, the data buses are formed of such number of data buses that is equal to the number of blocks obtained by dividing the first and second banks, and the data buses, respectively correspond to the blocks obtained by dividing the first and second banks.
When there are a large number of blocks obtained by dividing the banks, the data buses are formed of a large number of data buses and each data bus crosses a different crossing. Therefore, the area occupied by each data bus at each crossing can be suppressed.
Furthermore, a semiconductor integrated circuit according to the present invention includes first and second banks having a plurality of memory cells and capable of being driven independently, an input/output circuit arranged between the first and second banks and selectively writing/reading data to/from the plurality of memory cells included in the first and second banks, and a data bus inputting/outputting data through the input/output circuit.
In the semiconductor integrated circuit according to the present invention, the common input/output circuit selectively inputs/outputs data to/from the plurality of memory cells included in the first bank and the plurality of memory cells included in the second bank. Therefore, the number of data buses connected to the common input/output circuit can be minimized. As a result, the area occupied by the data buses can be suppressed.
Preferably, the input/output circuit includes an amplification circuit amplifying data from the plurality of memory cells included in the first or second bank, a driver outputting the data amplified by the amplification circuit to a data bus, a buffer inputting the data from the data bus to the plurality of memory cells included in the first or second bank, and a switch selectively connecting the amplification circuit to the first or second bank.
The amplification circuit outputting the data from the memory cells to the data bus as well as the buffer inputting the data from the data bus to the memory cells are selectively connected to the first or second bank by the switch. Therefore, the input/output circuit only has to be connected to the minimum number of data buses, and the area necessary for providing the data buses can be suppressed.
Preferably, the semiconductor integrated circuit further includes a first input/output line pair having one end connected to the first bank and the other end connected to the switch, and a second input/output line pair having one end connected to the second bank and the other end connected to the switch.
Data from a memory cell included in the first and second banks is transmitted to the switch through the first and second input/output line pairs. The data transmitted through the first input/output line pair or the data transmitted through the second input/output line pair is selectively input to the amplification circuit and the driver by the switch, amplified, and output to a data bus. The data from the data bus is transmitted to the switch through the buffer, selectively input to the first input/output line pair or the second input/output line pair by the switch, and written to a memory cell included in the first bank or a memory cell included in the second bank. Therefore, the input/output circuit only has to be connected to the minimum number of data buses, and the area necessary for providing the data buses can be suppressed.
Furthermore, a semiconductor integrated circuit according to the present invention includes a first data bus pair, a second data bus pair provided adjacent to the first data bus pair, a first bus driver outputting data from a first memory cell array to the first data bus pair, a second bus driver outputting data from a second memory cell array to the second data bus pair, a first potential rise prevention circuit provided between data buses of the first data bus pair and preventing potential rise of one data bus of the first data bus pair due to coupling from the second data bus pair when the second bus driver outputs data to the second data bus pair, and a second potential rise prevention circuit provided between data buses of the second data bus pair and preventing potential rise of one data bus of the second data bus pair due to coupling from the first data bus pair when the first bus driver outputs data to the first data bus pair.
In the semiconductor integrated circuit according to the present invention, adjacent two data bus pairs exist and, if data from a memory cell is output to one data bus pair, causing a potential difference between the data bus pairs, the potential rise preventing circuit prevents the potential of the other data bus pair adjacent to the data bus having a higher potential from rising due to coupling. Therefore, potential rise due to coupling can be prevented even if the interval between adjacent two data buses is made smaller. As a result, the area necessary for providing the data buses can be suppressed.
Preferably, the first potential rise prevention circuit is driven according to driving of the first bus driver, and the second potential rise prevention circuit is driven according to driving of the second bus driver.
Since the first or second potential rise prevention circuit is driven simultaneously with outputting of data from a memory cell to a data bus, the data can be correctly output to the data bus.
Preferably, the first and second potential rise preventing circuits are provided at prescribed intervals.
Since the interval of adjacent data buses is small, potential rise due to coupling is prevented even if a long data bus pair is provided. Therefore, a larger number of data bus pairs can be provided in a small area.
Preferably, a delay circuit is further included which generates a first bus driver delay signal obtained by delaying by a prescribed amount a first bus driver drive signal for driving the first bus driver, and a second bus driver delay signal obtained by delaying by a prescribed amount a second bus driver drive signal for driving the second bus driver. The first potential rise prevention circuit is driven according to the first bus driver delay signal, and the second potential rise prevention circuit is driven according to the second bus driver delay circuit.
After a prescribed time period has elapsed since the first and second bus driver outputting data from a memory cell to a data bus pair are driven, the first and second potential rise prevention circuits are driven. Therefore, a malfunction of the first and second potential rise prevention circuits can be prevented even if H level spike noise appears on a data bus on the lower potential side of the data bus pair.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.